Honored Contributor
Honored ContributorQuartus needs a timing constraint file. This is kind of advanced stuff. Timing constraint files for Quartus have the extension ".sdc" (synopsys design constraints). The language is TCL. The SDC constraints are very specific to each design. However, if you've based your design on one of the starter kit example designs, it should have an SDC file that you can use as a basis. You can use multiple SDC files on a single project.
Anyway, when you generated your SoPC system, it would have created an SDC file for the DDR interface. So what you'll want to do in Quartus is: 1 - Assignments->Settings->Timing Analysis Settings. Select the "Use TimeQuest Timing Analyzer....." radio button. 2 - Then on the left hand side of the pane, click "TimeQuest Timing Analyzer" under the "Timing Analysis Settings" section. Here is where you specify the SDC files for the project. Now you'll want to make sure you've got the SDC file for the DDR controller added in there. So browse and look for something like "...._phy_timing.sdc" and add that file to the project. And as I've mentioned, depending on how much you've changed your design from the example, design, you may want to add the sdc file included in the example design. Now when you compile your project in Quartus, the last step Quartus runs through is Timing Analysis. You can check the results to see if your design is meeting timing. If you want to educate yourself on TimeQuest: http://www.altera.com/support/software/timequest/sof-qts-timequest.html Jake
