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Most likely the sdram memory interface is either:
1 - Not properly connected
2 - Not meeting timing (or your not giving Quartus the timing constraints).
Jake
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Thanks for the info Jake!
1 - Properly connected as far as I know. Using the CIII Starter Kit connections verified in the pin planner. SOPC compiled without errors. Quartus compiled without errors.
2a - Not meeting timing...What is the easiest way to check this. I am assuming that SignalTap II Logic Analyzer will be able to help me determine this so I need to come up to speed on that regardless but if there is another quicker way to determine which timing spec is not being met than please do let me know.
2b- Not giving Quartus the timing contraints...I assumed I gave these values correctly in the DDR SDRAM High Performance Controller Core added in SOPC. I selected the memory I was using and did not see any reason why I should change the default timing parameters. Attached is where I am assuming I am giving Quartus the timing constraints. How do you give Quartus the timing contraints?
I am also going to play around with the System Library Property settings.
I just love solving a good mystery. This stuff is fun. :)
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