Forum Discussion
Honored ContributorSynthesis Problem
Hi everyone,
I have the following code worked fine:byte i, temp;
for (i=20; i>=0; i--)
begin
temp = i;
Array = array;
endbyte i, temp;
for (i=20; i>=0; i--)
begin
temp = i;
Array = arraytemp];
end9 Replies
Altera_ForumI am going to make an assumption that this is inside a clocked process (a little bit more info would be helpful).
When you run your for loop, the array index will always follow [i], so the result is: array[20]; .. array[19]; .. .. array[0]; but with your index as temp, you end up with temp = 20; .. temp = 19; .. .. temp = 0; In this case, temp is assigned multiple times, therefore temp will get the lower assignment (temp = 0). so you will end up with: Array[20] = array[0]; ... Array[19] = array[0]; ... Array[0] = array[0]; If this isn't it, more information on the code would be helpful.- Altera_Forum
Yes, this is inside a clocked process. I need to assign some value different from [i] of the for loop to the index of the array. How can I do that? :p
- Altera_Forum
The quick and dirty way would be to create a third array and use it to index array.
where index_array[] is an array of constants assigned outside your clocked process.byte i, temp; for (i=20; i>=0; i--) begin temp = i; Array = array]; end - Altera_Forum
Thank you. :D
- Altera_Forum
I am going to create another process for index_array[], and it should be complete right before the main process to be executed. I am wondering how to get to know the time it takes to complete the process. :rolleyes:
- Altera_Forum
hi,
I also have similar question related to this. I just want to type for i=0:5, f=i Thats it. So I tried for j in 0 to 5 loop assign f = i; end loop; Then it will give errors as Error (10170): Verilog HDL syntax error at Assignment.v(7) near text "for"; expecting an identifier ("for" is a reserved keyword ), or "endmodule", or a parallel statement Error (10170): Verilog HDL syntax error at Assignment.v(9) near text "end"; "end" without "begin" Can any one please help me? - Altera_Forum
1. Apparently you are trying to write Verilog. Why are you using VHDL loop syntax?
2. "Repeating" the same statement in a loop is completely meaningless 3. assign is a continuous statement. for() loop iterations are only allowed in sequential blocks. Generate loops can be used for continuous statements. 4. Review the details in a Verilog text book (presumed you are targeting to Verilog) - Altera_Forum
no i just want to know how for loop can write
thats why i mentioned f = i - Altera_Forum
Then forget about point 2 and refer to the others.
