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Altera_Forum
Honored Contributor
Honored ContributorSynthesis Problem
Hi everyone, I have the following code worked fine: byte i, temp;
for (i=20; i>=0; i--)
begin
temp = i;
Array = array;
end when I change it to: byte i, temp;
for (i=2...
Altera_ForumHonored Contributor
Honored Contributorhi,
I also have similar question related to this. I just want to type for i=0:5, f=i Thats it. So I tried for j in 0 to 5 loop assign f = i; end loop; Then it will give errors as Error (10170): Verilog HDL syntax error at Assignment.v(7) near text "for"; expecting an identifier ("for" is a reserved keyword ), or "endmodule", or a parallel statement Error (10170): Verilog HDL syntax error at Assignment.v(9) near text "end"; "end" without "begin" Can any one please help me?
