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Altera_Forum
Honored Contributor
Honored ContributorSynthesis Problem
Hi everyone, I have the following code worked fine: byte i, temp;
for (i=20; i>=0; i--)
begin
temp = i;
Array = array;
end when I change it to: byte i, temp;
for (i=2...
Altera_ForumHonored Contributor
Honored Contributor1. Apparently you are trying to write Verilog. Why are you using VHDL loop syntax?
2. "Repeating" the same statement in a loop is completely meaningless 3. assign is a continuous statement. for() loop iterations are only allowed in sequential blocks. Generate loops can be used for continuous statements. 4. Review the details in a Verilog text book (presumed you are targeting to Verilog)
