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Altera_Forum's avatar
Altera_Forum
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15 years ago

synthesis of VHDL module

is it possible to synthesis of VHDL module if there is integer variables in the VHDL module ?

-------------------------------

is it possible this module to be synthesized ? 


library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
entity clock is 
port  (
clk, reset: inout std_logic; 
fast_clk : inout std_logic ; 
d: in std_logic_vector(5 downto 0) ; 
Q :out std_logic_vector(16 downto 0);
enable : inout std_logic ; 
sec_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ;
min_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) 
);
end clock; 
architecture arch of clock is 
beginentity clock is 
port  (
clk, reset: inout std_logic; 
fast_clk : inout std_logic ; 
d: in std_logic_vector(5 downto 0) ; 
Q :out std_logic_vector(16 downto 0);
enable : inout std_logic ; 
sec_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ;
min_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) 
);
end clock; 
architecture arch of clock is 
begin
process   (clk, reset ) 
  VARIABLE sec : INTEGER  ;
  VARIABLE min : INTEGER  ;
begin 
  if (clk'event and clk = '1') then
  if (enable = '1') then 
    if (reset = '1') then sec  := 0 ; min := 0; end if;
      
       if (sec < 60) then sec := sec +1; else sec := 0; if ( min < 60) then min := min +1; else min := 0 ;  end if; end if ; 
  sec_bin<=CONV_STD_LOGIC_VECTOR(sec,6) ;
  min_bin<=CONV_STD_LOGIC_VECTOR(min,6) ;
    end if ;
  end if; 
end process;
end arch;

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Theres no problem with that, but I feer you're not quite going to get what you expect.

    Variables update immediatly, so sec_bin and min_bin are going to be the output of the adder direct rather than the output of the register holidng the values of sec and min.

    To prevent this, move sec_bin and min_bin assignments to be before the variable assignments.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    PS. why have you set clk, fast_clk, reset and enable ports to be inout rather than just in?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    so the code must look like this 

     
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
entity clock is 
port  (
clk, reset: inout std_logic; 
fast_clk : inout std_logic ; 
d: in std_logic_vector(5 downto 0) ; 
Q :out std_logic_vector(16 downto 0);
enable : inout std_logic ; 
sec_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ;
min_bin             : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) 
);
end clock; 
architecture arch of clock is 
begin
process   (clk, reset ) 
  VARIABLE sec : INTEGER  ;
  VARIABLE min : INTEGER  ;
begin 
    sec_bin<=CONV_STD_LOGIC_VECTOR(sec,6) ;
  min_bin<=CONV_STD_LOGIC_VECTOR(min,6) ;
  if (clk'event and clk = '1') then
  if (enable = '1') then 
    if (reset = '1') then sec  := 0 ; min := 0; end if;
      
       if (sec < 60) then sec := sec +1; else sec := 0; if ( min < 60) then min := min +1; else min := 0 ;  end if; end if ; 
    end if ;
  end if; 
end process; 
end arch ;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    no, keep the sec_bin and min_bin inside the clock assignments.

    The best thing for you to do is just test it and simulate it until it works