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Altera_Forum
Honored Contributor
Honored Contributorsynthesis of VHDL module
is it possible to synthesis of VHDL module if there is integer variables in the VHDL module ? ------------------------------- is it possible this module to be synthesized ?
librar...
Altera_ForumHonored Contributor
Honored ContributorPS. why have you set clk, fast_clk, reset and enable ports to be inout rather than just in?
