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Altera_Forum's avatar
Altera_Forum
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15 years ago

synthesis of VHDL module

is it possible to synthesis of VHDL module if there is integer variables in the VHDL module ? ------------------------------- is it possible this module to be synthesized ? librar...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Theres no problem with that, but I feer you're not quite going to get what you expect.

Variables update immediatly, so sec_bin and min_bin are going to be the output of the adder direct rather than the output of the register holidng the values of sec and min.

To prevent this, move sec_bin and min_bin assignments to be before the variable assignments.