Synchronous, asynchronous and synchronous asynchronous reset

Hello,

I guess this question was discussed quite often but I'm still a little bit lost here.

As far as I understood it Altera and also Xilinx are recommending synchronous asynchronous reset generation. This means the reset signal gets asserted asynchronously and deasserted synchronously.

My question is how should I implement the reset mechanism in my designs for the components which should be reset be the signal? I've created a component which triggers synchronously reset and a component which trigger asynchronously to the reset signal. Looking at the result in the Technology Map Viewer it looks like that an asynchronous reset logic is fitting better to the technology Altera uses.

Here is the example which Xilinx recommends for the reset logic (they have a document called libguide.pdf where one can look up the preferred coding style for logic elements):

process (clk)

begin

if clk’event and clk=’1’ then

if reset=’1’ then

data_out <= ’0’;

else

if force_high=’1’ then

data_out <= ’1’;

else

if enable=’1’ then

data_out <= a and b and c and d;

end if;

end if;

end if;

end if;

end process;

Does a similar document exist for Altera devices?

Best regards

Martin