Synchronous, asynchronous and synchronous asynchronous reset

Tricky is right in that Altera register's have an asynchronous reset and if you don't use it, it's wasted. Making your reset synchronous will have that signal compete with other synchronous inputs, making the design a little larger and possibly slower. That being said, TimeQuest will analyze the signal feeding the asyncrhonous input of a register in a synchronous manner, which is called recovery and removal analysis. Look at Recovery and Removal on page 65 of the following guide:

http://www.alterawiki.com/wiki/timequest_user_guide

As explained, the recommendation is to build an asynchronous assert, synchronous de-assert circuit(it's only 2 registers). That gives you the benefits of an asynchronous reset but allows static timing analysis to look at the de-assertion and make sure everything in the system comes out of reset on the same clock. (I've found many companies, ASIC designers, etc. hav similar recommendations...)