synchronize pll

Look at:

I think, the only suitable solution to synchronize a clock to single pulse is a digital PLL created in your design. But the timing resolution is limited by the reference clock, could be up to 300 or 400 MHz with cyclone II.

Where is the pulse coming from that would start your state machine? How do you intend to phase align your 50 MHz clock with the 10MHz clock that the A/D is using?

It is from external equipment. This trigger pulse is latched by 50Mhz logic. After latching, the very next clock starts the state machine. I will probably use the digital pll method suggested, or just generate the 10Mhz clock from the 50mhz logic. Counters are simple.

Yes, starting a :5 clockdivider on the start pulse would be the most simple solution. (In case of a single start pulse, a digital PLL can't do anything more). As an disadadvantage, the clock divider output has more jitter than an analog PLL output. This would be a problem only in applications, where a input waveform has to be reconstructed from samples, e. g. digital receivers or FFT processing of input data, where the aperture jitter is converted in an amplitude uncertainty respectively additional noise. Also the clock output delay has to be considered when defining the ADC data read timing. Processing of AD data should be performed in the 50 MHz domain with a 10 MHz clock enable.

The DDIO megafunction could be used along with a small state machine to generate a 10MHz clock off the 50MHz clock. tco of the DDIO is very small and an indicator of the rising edge of the 10MHz generated clock could be used in the 50MHz domain. This would allow the 50Mhz domain to know the phase of the 10MHz domain generated by the DDIO. All logic would stay in the 50Mhz domain.

Depending on the used ADC, it may be operational also with 40 or 60% duty cycle clock, so the somewhat more complex DDIO solution won't be necessary. Another point is, that the ADC may have a startup time after applying the clock and possibly show a transitional reaction after shifting the clock phase.

This A/D does need close to 50% duty, so some of the circuit options won't work. The odd divider needs both pos and neg edge switching as the DDIO would use. I don't see any cyclone primitives with negative clocks so I wonder how they do that one and still be symmetrical. I'll try it if I can figure out how.

DDIO configured as a single bit output. Write a small state machine to send 1's to datain_h and datain_l for two 50 MHz cycles. Then send datain_h a '1' and datain_l a '0' on the next 50MHz cycle. For the final two 50MHz cycles, send datain_h and datain_l zeros. Just repeat this and you have a pretty good 10MHz clock based on the 50MHz clock. Constrain the DDIO output with tco and tco_min(or is it min_tco). This method would allow you to not run the 10MHz DDIO clock until you see the pulse telling you to do the A/D conversions, thus avoid having to wait for then next rising edge of a free running 10MHz clock.

How would you get this functionality if you had to write the verilog? It seems you can't just say @(posedge clk or negedge clk). You'd have to have one clause for each edge and interleave them - but how?