Honored Contributor
Honored ContributorDDIO configured as a single bit output. Write a small state machine to send 1's to datain_h and datain_l for two 50 MHz cycles. Then send datain_h a '1' and datain_l a '0' on the next 50MHz cycle. For the final two 50MHz cycles, send datain_h and datain_l zeros. Just repeat this and you have a pretty good 10MHz clock based on the 50MHz clock. Constrain the DDIO output with tco and tco_min(or is it min_tco). This method would allow you to not run the 10MHz DDIO clock until you see the pulse telling you to do the A/D conversions, thus avoid having to wait for then next rising edge of a free running 10MHz clock.
Add in a signal that lets your control logic(running in the 50MHz domain) know when the rising edge of the 10MHz DDIO clcok happens and you can control the A/D in the 50Mhz domain and still run the A/D at 10Mhz. I do not think this is a complex solution, it is just sound synchronous design to achieve the requirements. Only you know what your requirements are so you'll have to choose the best solution.
