synchronize pll

Yes, starting a :5 clockdivider on the start pulse would be the most simple solution. (In case of a single start pulse, a digital PLL can't do anything more). As an disadadvantage, the clock divider output has more jitter than an analog PLL output. This would be a problem only in applications, where a input waveform has to be reconstructed from samples, e. g. digital receivers or FFT processing of input data, where the aperture jitter is converted in an amplitude uncertainty respectively additional noise. Also the clock output delay has to be considered when defining the ADC data read timing. Processing of AD data should be performed in the 50 MHz domain with a 10 MHz clock enable.