synchronize pll

The Quartus Handbook clarifies that DDIO can't be inferred from HDL code:

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You must instantiate megafunctions to target certain device and high-speed features such as LVDS drivers, PLLs, transceivers, and double-data rate input/output (DDIO) circuitry.

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Other solutions that combine posedge and negedge clocked registers are possible, but you have to take care not to generate glitches. One option is to use a asynchronous clear from a register clocked at the opposite edge. See: http://www.edaboard.com/viewtopic.php?t=303735