synchronize pll

This short code works pretty well. Functional sim looks perfect but timing sim does not init properly. On CII grade8, a 50mhz:10mhz conversion has 50% duty. I don't see glitches, but it does not always start aligned to the 1st rising edge like I want. Could be improved.

--- Quote Start ---

module ddrdiv5_clk

(

clk50,

nReset,

cnt_en,

clk10_out

);

input clk50;

input nReset;

input cnt_en;

output clk10_out;

reg[4:0] ddsrh;

reg[4:0] ddsrl;

reg first;

assign clk10_out = ddsrh[0] & (ddsrl[0] | ~ddsrh[4] | ~ddsrl[4]);

always @(posedge clk50 or negedge nReset)

begin

if(!nReset)

begin

ddsrh[4:0] <= 5'b01110;

first <= 1'b0;

end

else

begin

if(cnt_en)

begin

ddsrh[4:0] <= {ddsrh[0],ddsrh[4:1]};

first <= 1'b1;

end

else

begin

ddsrh[4:0] <= ddsrh[4:0];

end

end

end

always @(negedge clk50)

begin

if(!first)

begin

ddsrl[4:0] <= 5'b00110;

end

else

begin

if(cnt_en)

begin

ddsrl[4:0] <= {ddsrl[0],ddsrl[4:1]};

end

else

begin

ddsrl[4:0] <= ddsrl[4:0];

end

end

end

endmodule

--- Quote End ---