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in your case I am not surprised that asynchronous application was safer because it bypassed the clk edge.
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Well, it only bypasses the clock edge on assertion, not deassertion, hence the need for a synchronizer. Which, again, was why I was confused as the problem seemed to be introduced on deassertion, where async reset is even more picky than sync reset.
I finally took a deep breath and untangled the result of synthesis, and the behavior was indeed coming from a race condition on reset deassertion introduced by modeling the RTL
always @ (posedge clk)
if (!rst_n)
A <= 1'b0;
else if (trigger)
A <= B;
by the resource with
clk = clk;
D = rst_n & B;
ena = !rst_n | trigger;
So, I get the wrong reset state when the deassertion of rst_n is seen on the data path a cycle before the enable. The synthesis result for the asynchronous case just uses the sclr port and so has no race condition. Mystery solved.
Honored Contributor
