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Overall, I would expect synchronous reset to be *more* robust than asynchronous reset, not less, without any synchronization.
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Both are unreliable
without any synchronization. The specific behaviour depends on the design details, that haven't been shown in the present case. I don't want to guess, why the synchronous example appears less realiable to you. Because both need synchronization, I won't suggest to use synchronous constructs for the general design reset. The asynchronous variant has the important advantage to achieve defined output states without applying a clock, which is mandatory in many designs. Because it uses dedicated clear inputs of the FPGA registers, it saves resources compared to the synchronous solution.
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As such, my question is about understanding the underlying problem I'm seeing, not how to work around it.
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Synchronization of unrelated signals in
not a workaround. It's simply required, for
both reset variants.
Honored Contributor
