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Altera_Forum
Honored Contributor
Honored ContributorSync reset with push-button not reliable
I'm using Quartus II 9.1 Web Edition with a DE1 (Cyclone II Starter Kit) board and I have some problems with resetting my tiny design that I can't figure out. When I have all my flops reset synchrono...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Overall, I would expect synchronous reset to be *more* robust than asynchronous reset, not less, without any synchronization. --- Quote End --- Both are unreliable without any synchronization. The specific behaviour depends on the design details, that haven't been shown in the present case. I don't want to guess, why the synchronous example appears less realiable to you. Because both need synchronization, I won't suggest to use synchronous constructs for the general design reset. The asynchronous variant has the important advantage to achieve defined output states without applying a clock, which is mandatory in many designs. Because it uses dedicated clear inputs of the FPGA registers, it saves resources compared to the synchronous solution. --- Quote Start --- As such, my question is about understanding the underlying problem I'm seeing, not how to work around it. --- Quote End --- Synchronization of unrelated signals in not a workaround. It's simply required, for both reset variants.
