Sync reset with push-button not reliable

Hi sanmao,

Thanks for the pointer to the tech note. The general discussion looks like a verbatim copy of Cummings' and Mills' paper (indeed my synchronization was taken from there), but I'll be sure to revisit it for FPGA specific hints when I start implementing more complicated designs.

As for the overall discussion, I now realize my original question was not clear: The question was not why I'm getting reset problems when using synchronous resetting without synchronizing the reset signal (although I'm frankly baffled at the frequency of errors), but rather why I'm not seeing the same problems with asynchronous reset (without synchronizing the reset signal). As such, my question is about understanding the underlying problem I'm seeing, not how to work around it.

Since I'm pulling reset with the touch of my finger, reset is pulled for 100's or 1000's of cycles, so any non-determinism (label it meta-stability or anything else you want) at the assertion of reset should be irrelevant. Indeed, the reset state is perfectly fine *during* reset. Neither "trigger" nor "ms_timeout" will change for 1000's of cycles after reset, so they shouldn't be able to cause any issues and should make it impossible for a0_next to "get to" a0 anytime around reset. By the same reasoning, I don't see any reason why glitches on the reset signal would cause any trouble once the reset state is set.

Overall, I would expect synchronous reset to be *more* robust than asynchronous reset, not less, without any synchronization. The case against sync reset, as I read it, is about gate count and therefore setup time, not robustness.

Thanks for all the responses so far, I really appreciate them!

Sebastian