Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI completely agree with your explanation of the problem that rst_n is "misinterpreted by different flip-flops", if the "transition of the reset signal comes at the moment of the clock edge". But as you said, that's not metastability.
The solution is synchronization of the unrelated signal to CLOCK_50:always @ (posedge CLOCK_50)
rst_n_sync <= rst_n;
if (!rst_n_sync) begin
a3 <= 4'b0;
a2 <= 4'b0;
a1 <= 4'b0;
a0 <= 4'b0;
end
else if (trigger & !done & ms_timeout) begin
a3 <= a3_next;
a2 <= a2_next;
a1 <= a1_next;
a0 <= a0_next;
end I should be mentioned, that if other signals, e.g. trigger would be unrelated to CLOCK_50, they also need to be synchronized. Metastability describes the (very unlikely, but still existing) case, that rst_n_sync hasn't reached a defined logic state after one cycle of CLOCK_50. Quartus has a metastability advisor, that calculates the likelihood of metastable states for particular synchronizers. If the possible faulty behaviour due to metastability is a risk for the application, a multistage synchronizer can reduce the likelihood to effectively zero. In the present case, I guess, that the lifetime of a the mechanical switch would be exceeded before metastability induces MTBF is reached. But if the signal to be synchronized is switching very often, e.g. it's a MBPS serial signal, a metastable event can be expected in a very finite period of time.