Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi FvM,
when using an external button or switch for reset, the reset signal is unrelated to the clock. Of course it depends on the delay paths from your reset button to the flip-flops where it is being used and of course the relationship to the clock edge where the reset signal is used. So depending on when you reset in relation to your clock edge, even with synchronized resets, the chances are very real that this transition of the reset signal comes at the moment of the clock edge. Or that some paths of the (synchronous) reset signal may arrive earlier and other later than the clock edge. This is not usually what you want and it can mean that your system does not synchronously reset all flip flops at the same time. It is not difficult to make such a system, even with synchronous resets (from a button or switch) as you mention. I (mis)use the term metastable to indicate that we are in such cases operating on the border of what has to be recognized in one way or another, as the -synchronous- reset signal can arrive from the unrelated button input at nearly the same time (or before or after) the clock edge. To make real synchronized reset signals the method of
always @(posedge clock)
if (!rst_n)
... blah blah blah
is not reliable enough when using switches or buttons, because the chance that the transition happens very near to the clock edge is very likely (Giving the results of the first poster). In order not to repeat things, I only wanted to refer to an excellent white paper in a previous thread of the forum. Hope this clarifies my abuse of metastability... --- Quote Start --- I think, it's misleading to use the term "metastability" for trivial cases of timing violation caused by unrelated input signals. But synchronizing the input signal (in this case rst_n) to the clock is the appropriate means anyway. --- Quote End ---