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Altera_Forum
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16 years ago

Sync reset with push-button not reliable

I'm using Quartus II 9.1 Web Edition with a DE1 (Cyclone II Starter Kit) board and I have some problems with resetting my tiny design that I can't figure out. When I have all my flops reset synchrono...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Sebastian,

both the direct synchronous as well as asynchronous can have problems with metastability. This means the acceptance or not of your reset near the rising edge of your clock signal. This can be misinterpreted by different flip-flops in your FPGA, giving the results that you describe.

Please refer to thread: http://www.alteraforum.com/forum/showthread.php?t=4281 which has a nice paper explaining how to make a good reset circuit in general and for Altera in particular.

Hope this clarifies a little,