Forum Discussion
Altera_Forum
Honored Contributor
16 years ago
always @ (posedge CLOCK_50)
if (!rst_n) begin
a3 <= 4'b0;
a2 <= 4'b0;
a1 <= 4'b0;
a0 <= 4'b0;
end
else if (trigger & !done & ms_timeout) begin
a3 <= a3_next;
a2 <= a2_next;
a1 <= a1_next;
a0 <= a0_next;
end
You have stated that above code implies synchronous reset. but is your reset signal itself synchronised from origin? Synchronous reset is true only if it is sourced synchronously. Applying it synchronously is not enough by itself. It may for example bounce at the key in your case. Also mak sure that timing is not violated and you may delete your signaltap file and restart fresh.