Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

switching between CMU PLLs 0 and 1

I have been through AN558 Dynamic reconfiguration for ArriaIIGx and the documentation to do with the transceivers but I can't extract what I am looking for.

I want to switch the CMU PLL a transceiver block is listening to from CMU PLL0 to CMU PLL1. I believe I have everything setup as I should do in the altgxb block and the altgxb_reconfig block. I have the alternative PLL setup in the altgxb block as well. I am just a bit unsure how you actually switch between the PLLs.

Do you have to write out the mif and then use a rom to reconfigure the PLLs?? Its just the CMU plls know what they should be. I only want to switch between the two of them.

I have tried using logical_tx_pll_sel and then hitting pulsing 'write all' but nothing happens. I have 'reconfig_mode_sel = 110'.

I don't need to do any channel reconfiguration as I am actually using the transceiver I want to reconfigure as a clock output to feed another gxb as I have run out of plls

Any help would be gratefully received

C

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Finally figured it out by attrition :mad:.

    I still don't know if there is an easier way to switch between CMU PLLs but here is way I did it.

    1) You setup a gxb reconfig block, a gxb block and two roms.

    2) There is enough information in AN558 to allow you to setup the reconfig block and the gxb.

    3) The part I was missing was I had setup the gxb with a main pll and alternative pll and I thought you could just switch between the two some how. What you need to do write out a .mif with the PLL settings you want the gxb to listen to initially set as the main pll. For example set main pll as 108 MHz clock and the alternative pll setup as a 162MHz clock. You then create a second .mif with this switched over so main pll is now 162MHz clock and alternative is 108MHz clock. Making sure that when you switch them over, the logical number and the input source of the clock follows it. So I set the 108MHz as having a logical number of 0 and input port 0. When I switched it over to the alternative pll, these numbers followed the clock.

    4) Put the .mifs inside roms and connect them to the reconfig block using a mux on the data. Use a signal to select between which clock you want.

    5) The last thing to do it is set pll sel mode to 100 or 101. Mode 110 doesn't do anything when you try and reconfigure the PLLs. I think mode 110 is for switching over the plls but I just don't know how to control that mode.

    Hope someone else finds this experience useful :)

    C