Stratix10 SoC using FPGA fabric U-Boot failed to reset or stuck at DDR initialization

Question

Hi expert,
I am using Quartus 21.3 to generate a *_hps.sof for Stratix10 SoC, but arm stuck at DDR initialization when finishing loading *_hps.sof
gsrd is：https://rocketboards.org/foswiki/Documentation/S10GSRDV180UserManual?erpm_id=1936756_ts1650518835963
Use pfg to generate *_hps.sof from .sof
Arm log is:
U-Boot SPL 2017.09 (Mar 27 2019 - 09:31:09)MPU 1200000 kHzL3 main 400000 kHzMain VCO 2400000 kHzPer VCO 2000000 kHzEOSC1 25000 kHzHPS MMC 50000 kHzUART 100000 kHzDDR: Initializing Hard Memory ControllerDDR: Calibration successSDRAM: Initializing ECC 0x00000000 - 0x80000000SDRAM-ECC: Initialized success with 1343 msDDR: HMC init successDDR: 2048 MiBDDR: Running SDRAM size sanity check"Synchronous Abort" handler, esr 0x96000210ELR: ffe042dcLR: ffe01950x 0: 0000000001000000 x 1: 0000000080000000x 2: 0000000008000000 x 3: 0000000000000003x 4: 0000000000000000 x 5: 00000000ffe3dc68x 6: fffffffffdffffff x 7: 0000000010000000x 8: 0000000000000031 x 9: 0000000000000080x10: 00000000000004f4 x11: 0000000000000074x12: 0000000000000002 x13: 0000000000000023x14: 0000000000000008 x15: 0000000000000008x16: 0000000000030a0f x17: 75c33a83711ebed7x18: 00000000ffe3de90 x19: 00000000ffe3de90x20: 00000000ffd21000 x21: 00000000ffffffffx22: 00000000ffd12000 x23: 0000000000000000x24: 00000000ffe2a000 x25: 00000000fffffff7x26: 0000000000000001 x27: 0000000000004000x28: 0000000000000002 x29: 00000000ffe3de60
Resetting CPU ...
resetting ...Mailbox: Issuing mailbox cmd REBOOT_HPS

I Change to another u-boot hex: https://releases.rocketboards.org/release/2020.05/gsrd/s10_gsrd/u-boot-spl-dtb.hex

arm log is:
U-Boot SPL 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)Reset state: ColdMPU 1200000 kHzL3 main 400000 kHzMain VCO 2400000 kHzPer VCO 2000000 kHzEOSC1 25000 kHzHPS MMC 50000 kHzUART 100000 kHzDDR: Warning: DRAM size from device tree mismatch with hardware.DDR: 4096 MiB

Anything wrong with my step?
And additional question is why the size of *_hps.sof is much smaller than *.sof？

eberlazare_i_intel · Answer

Hi,Are you using a S10 Dev Kit?I recommend to use the new build flow to get the latest U-boot version:https://rocketboards.org/foswiki/Documentation/BuildingBootloaderThe hps.sof contains the FPGA configuration info, as well as the HPS U-boot FSBL code and HPS FSBL hardware Handoff binary.The .sof contains the necessary handoff file information that is required by the First-Stage Bootloader (FSBL) during boot up, such as HPS clock and pin mux information.

jiayi_h_intel · Answer

I am using S10 SoC Dev Kit.
May I know if there is any gsrd with uboot in it, which can support S10 SoC Dev Kit with1SX280HU2F50E1VGAS device?
Does hps.sof includes all FPGA customer design logic since it is so small?

eberlazare_i_intel · Answer

Hi,Here is the pre-built images you can find of various versions:https://releases.rocketboards.org/release/This is using SD Card:https://releases.rocketboards.org/release/2021.04/gsrd/s10_gsrd/The link I provided previously, is to create the images, the link above has the pre-built images which you can program and write to your board and boot it up.

eberlazare_i_intel · Answer

Hi,Do you have any further questions?

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Stratix10 SoC using FPGA fabric U-Boot failed to reset or stuck at DDR initialization

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