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Jiayi_H_Intel's avatar
Jiayi_H_Intel
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Stratix10 SoC using FPGA fabric U-Boot failed to reset or stuck at DDR initialization

Hi expert, I am using Quartus 21.3 to generate a *_hps.sof for Stratix10 SoC, but arm stuck at DDR initialization when finishing loading *_hps.sof gsrd is：https://rocketboards.org/foswiki/Documen...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Are you using a S10 Dev Kit?


I recommend to use the new build flow to get the latest U-boot version:

https://rocketboards.org/foswiki/Documentation/BuildingBootloader


The hps.sof contains the FPGA configuration info, as well as the HPS U-boot FSBL code and HPS FSBL hardware Handoff binary.


The .sof contains the necessary handoff file information that is required by the First-Stage Bootloader (FSBL) during boot up, such as HPS clock and pin mux information.


Jiayi_H_Intel's avatar
Jiayi_H_Intel
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I am using S10 SoC Dev Kit.

May I know if there is any gsrd with uboot in it, which can support S10 SoC Dev Kit with1SX280HU2F50E1VGAS device?

Does hps.sof includes all FPGA customer design logic since it is so small?