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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi allen18,

As there are no further inquiries, I will transition this thread to community support.

If you have a new question, feel free to open a new thread to get support from Altera experts.


Thanks.

Best Regards,

Ven