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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
9 months ago

Hi allen18,


My apologies for the late reply.


I have uploaded the project .qar file. This is the Gen3 x4 design example that was generated from the .ip file you sent earlier.


Thanks.

Best Regards,

Ven


*Kindly take note that 31 Mar and 1 Apr 2025 are national public holidays, please expect a delay in response.