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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi allen18,


Thank you for the reply.


The Design Example I generated was using a rather new version of the QPDS Pro, v24.3. I will generate the Design Example using v22.3 so that you can test it in your environment. Do you have a Stratix 10 Dev Kit to test it with?

Please kindly wait for a while, I will attach the .qar later.


Thanks.

Best Regards,

Ven