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allen18's avatar
allen18
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1 year ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
11 months ago

Hi allen18,


Could you please share the .ip file so that I can generate the Design Example based on your settings?


Thanks.

Best Regards,

Ven


allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Hi ventt,

The attachment is my IP file. To ensure example design generate successfully, I don't think it's necessary to keep all settings consistent as mine. Just set the slot clock configuration to OFF and use a separate PCIe reference clock.

Thinks.