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allen18
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10 months ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Hi ventt,

My reference clock comes from a crystal oscillator, which has a frequency of 100MHz , not the OSC-IN pin, OSC-IN connected to another 125MHz crystal oscillator.

As shown in the figure, AV33,AV34,The common clock, connected to PC board via oculink. AT33, AT34 come from a crystal oscillator on FPGA board. AV33,AV34, This set of clocks is working normally. If I connect to AT33, AT34, Will not work properly and print errors.

Please help investigating why the latter set of clocks is not working properly.

Thanks.