New Contributor
Super ContributorGlobal Signal assignments only controls whether a signal is promoted using the specified dedicated resources or not, but does not control which or how many resources are used.
To take full advantage of the routing resources in a design, make sure that the sources of clock signals (input clock pins or internally-generated clocks) drive only the clock input ports of registers
New ContributorHi SyafieqS_intel,
Will assigning a virtual pin to a dedicated CLK pin solve the problem?
Is the GCLK allocation method different between Stratix10 and Arria10 due to the difference in clock resources?
