Stratix V GT tranceivers with unmodified output

Hi Neil,

What are you trying to modulate at 20GHz?

You cannot avoid using the serializer features in the SERDES. But that is what you want right? You create a parallel output PRBS pattern in the FPGA fabric, and then send that to the SERDES to be serialized to 1-bit and output at whatever data rate you have decided.

I have this requirement for a Hittite ADC, i.e., to generate a 10GHz or 20GHz XOR modulation pattern. The problem with trying to use an FPGA, is that its transmitter output delay is not defined (try finding it in the device handbook or datasheet). That means any temperature change in the FPGA could affect the transmitter output in an arbitrary manner. My "solution" was to use a 10Gbps XFP PHY (SiLabs Si5040). The modulation pattern is only 10Gbps, but for this Hittite ADC, the XOR pattern is for the output data lanes, which run at 10Gbps, so the SiLabs PRBS is ok.

Here's some documentation that may be of interest:

LFSR/PRBS generation:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

Hittite ADC development:

http://www.ovro.caltech.edu/~dwh/wbsddc/

Cheers,

Dave

Ahh the old nomenclature mix up trick....Indeed I do of course want a serial stream.

Thanks Dave,

Since the GT transceivers only use the PMA, all the PCS encoding is bypassed, I see that. So then does the PMA add any ecoding at all? If not, then the parallel data does come out unadulterated, and I may have a dev board for my problem.

Transmitter delay will not be a problem. The modulation is for an optical link that we want to test and deserialisation will not occur, hence the reason for not wanting any encoding. Once "booted" the tx will run constantly for some arbitrary amount of time.

Regards,

Neil.

Hi Neil,

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Ahh the old nomenclature mix up trick....Indeed I do of course want a serial stream.

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Ok, then the transceiver will work fine.

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Since the GT transceivers only use the PMA, all the PCS encoding is bypassed, I see that. So then does the PMA add any ecoding at all? If not, then the parallel data does come out unadulterated, and I may have a dev board for my problem.

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You can configure the transmitter to send what you have supplied from the fabric.

You can still enable transmit pre-emphasis and adjust the transmitter eye opening (I've used this in Stratix IV GT, not V, but it should be similar).

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Transmitter delay will not be a problem. The modulation is for an optical link that we want to test and deserialisation will not occur, hence the reason for not wanting any encoding. Once "booted" the tx will run constantly for some arbitrary amount of time.

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Great, your application can deal with arbitrary delays.

Take a look at the LFSR/PRBS tutorial I linked to, you can use the code that comes with it. Take a look at the Hittite ADC hardware test doc,

http://www.ovro.caltech.edu/~dwh/wbsddc/hittite_adc_hw.pdf

and you'll see a setup (Qsys system setup as an ADC simulator) that does exactly what you want. You can create your own Stratix V version. The design can be simulated first; create both a transmitter and receiver design and that way you can convince yourself that the link receiver will work correctly. In your hardware setup you can use a BERT tester with the same PRBS setup and it will work fine (the engineers at Hittite setup some tests like this).

Cheers,

Dave