Honored Contributor
Honored ContributorHi Neil,
What are you trying to modulate at 20GHz? You cannot avoid using the serializer features in the SERDES. But that is what you want right? You create a parallel output PRBS pattern in the FPGA fabric, and then send that to the SERDES to be serialized to 1-bit and output at whatever data rate you have decided. I have this requirement for a Hittite ADC, i.e., to generate a 10GHz or 20GHz XOR modulation pattern. The problem with trying to use an FPGA, is that its transmitter output delay is not defined (try finding it in the device handbook or datasheet). That means any temperature change in the FPGA could affect the transmitter output in an arbitrary manner. My "solution" was to use a 10Gbps XFP PHY (SiLabs Si5040). The modulation pattern is only 10Gbps, but for this Hittite ADC, the XOR pattern is for the output data lanes, which run at 10Gbps, so the SiLabs PRBS is ok. Here's some documentation that may be of interest: LFSR/PRBS generation: http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip Hittite ADC development: http://www.ovro.caltech.edu/~dwh/wbsddc/ Cheers, Dave
