Stratix IV OCT help

I'm having some problems instantiating the OCT megafunction in my design. I started with the DDR2 memory controller which has 2 inputs: oct_ctl_rs_value and oct_ctl_rt_value. So I instantiated an OCT megafunction with calibration on power up which has the following 4 pins.

component oct is

port (

rdn : in std_logic_vector( 0 downto 0);

rup : in std_logic_vector( 0 downto 0);

parallelterminationcontrol : out std_logic_vector(13 downto 0);

seriesterminationcontrol : out std_logic_vector(13 downto 0)

);

end component oct;

I connected the seriesterminationcontrol to the oct_ctl_rs_value and the parallelterminationcontrol to the oct_ctl_rt_value. rdn and rup are connected to 2 signals at the top level of my vhdl. In my QSF file, I've assigned the rdn and rup pins. When I attemp to compile my design I get a error that the OCT block can not be placed because the "termination_blk0~_rdn_pad" and the "termination_blk0~_rup_pad" locations are already used. Is the tool promoting the these two pins to the top level instead of using the "rdn" and "rup" pins I assigned?

What is the correct way to instantiate the OCT block?

Thanks

Andy