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Altera_Forum
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15 years ago

Stratix IV GX altgx reconfiguration

I've got a project that I'm porting from Stratix II GX to Stratix IV GX. Basically I'm using all the transceivers in a Quad. I'm using both TX PLLs in the Quad. I need to dynamically select which PLL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Jake,

Did you ever resolve this issue? I am having a similar problem with a Stratix IV ALTGX transceiver. But I'm not sure if I'm putting in the correct timing constraints in the first place. I just put a constraint on the input ref clk and then do "derive_pll_clocks". Is that what you're doing?

I notice there only seems to be one tx_clkout signal when I have five channels and am expecting five tx_clkout signals.

Does anyone have experience with this?