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Havana's avatar
Havana
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6 years ago

Stratix III: Pull up resistor at open drain output to voltage higher than VccIO

Hello,

I need to generate some slow 3.3V output signals at the GPIOs of my Stratix III on a bank which uses 2.5V VCC_IO. I have to use this voltage because I need LVDS inputs/outputs von these banks. And unfortunately, I have no chance to place these signals on an other bank.

Is it possible/allowed to use a pull-up resistor to 3.3V if my output is configured as open drain? I haven’t found any information about the maximum voltage at an open drain output.

The recommended Operating Condition says DC Input Voltage V_I(max) = 3.6V (1-4). For “2.5-V LVTTL/ LVCMOS”-inputs I found V_IH(Max) = 3.6V (1-9).

The Table 7-7 on Chapter 7 p19 allows 3.3V input voltages if the PCI clamp diode is activated. But I don’t want to limit my output voltage to 2.5V+V_diode.

Thanks for any advice.

1 Reply

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Is it possible/allowed to use a pull-up resistor to 3.3V if my output is configured as open drain? Yes , But make sure the R Choosen correct so that current is limited .

    I dont understand why you want compare the input specification for output buffer above VCCIO ?

    Thank you ,

    Regards,

    Sree