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Havana's avatar
Havana
Icon for New Contributor rankNew Contributor
6 years ago

Stratix III: Pull up resistor at open drain output to voltage higher than VccIO

Hello, I need to generate some slow 3.3V output signals at the GPIOs of my Stratix III on a bank which uses 2.5V VCC_IO. I have to use this voltage because I need LVDS inputs/outputs von these banks...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Is it possible/allowed to use a pull-up resistor to 3.3V if my output is configured as open drain? Yes , But make sure the R Choosen correct so that current is limited .

I dont understand why you want compare the input specification for output buffer above VCCIO ?

Thank you ,

Regards,

Sree