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Altera_Forum's avatar
Altera_Forum
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16 years ago

Stratix III LVDS OCT

Hello!

I am using stratix III and I have a few questions about LVDS and OCT in stratix III and I/O buffers.

1. If we want to use dynamic termination, can we use differential mode?

a. Is it only possible to use dynamic termination in single-ended mode as stated in the documentation?

b. If the dynamic termination is just for single ended buffers, why there is an option to choose the dynamic termination in megawizard function with bidirectional differential IO buffer?

2. In BLVDS, it states that for receiver side differential input buffer and the transmitter side 2 single ended buffers are used. Therefore, is not it possible to use bidirectional differential buffers for LVDS?

3. How do we use differential OCT?

Is it possible to turn OCT on and off while operating ( according to write and read cycles - transmitter and receiver operation)?

4. In ALTOCT block and ALTIOBUF, what are the bit values(14 bits) for the parallel and series termination? Where can I find the details?

Thanks for your answers.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    I have been studying this area recently and so I am unsure as you are and hope the gurus will step in. Here are my views:

    1) my understanding is that LVDS needs parallel 100 ohm at input only. It does not need anything else. Remember LVDS is one type of differential io

    standards. Since output drivers don't need termination with LVDS then you don't need to think of dynamic OCT.

    2) Some other differential schemes use two single ended lines and need their own termination. I believe dynamic OCT applies here.

    3) already answered.

    4) the 14 bits are control words that are generated by altoct and fed into altiobuf.

    You can study altoct and altiobuf user guide examples. Both modules are used together as pair to do OCT with calibration or dynamic OCT
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    I know that we just need the termination in the receiver side but i am using two fpgas and they communicate over the same differential pair.

    I have transmitter and receiver (transceivers) in both fpgas and i am using bidirectional io buffer in differential mode, therefore I don`t want to have a permanent resistance of 100 ohm in each side. because then i have a 50 ohm equivalent, which is not the case that I want.

    I think it is not possible to have dynamic termination for LVDS, so may be the best solution is to use external termination that can be turned on and off.

    Thanks for your prompt reply.

    I will be happy to hear other ideas and replies.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Even with two fpga you still need 100 ohm at each input pairs of buffers. When one fpga outputs to the other the 100 Ohm at sender is irrelevant since it is across the input buffers.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    But the current passing through the differential pair doubles (4 mA to 8 mA) with the case of one 100 ohm but the signal is not affected as you say. the problem is that the power consumption increases in that case.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Fair enough, if you are concerned about 4mA being wasted when your fpga is in output mode then as you said an external termination resistor with a switch from fpga will do the trick.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Just did a quick compilation on stratix III with bidirectional pins in LVDS mode. It does not allow lvds for bidir pins

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    By design, BLVDS is using a party line, 100 ohm terminated at both ends. This is the only way to achieve impedance matching in a multidrop bus topology. Dynamic OCT wouldn't be helpful in this situaion.

    I understand, that you intend a bidirectional point-to-point connection, in this case differential dynamic OCT would be an option. I think that it's provided with Stratix III, but no tri-statetable true LVDS driver. Pseudo-differential operated single-ended buffers with serial termination have to be used instead.

    P.S.: For Stratix III, Quartus doesn't offer a BLVDS I/O standard in Pin Planner. Diff. SSTL has to be used instead. See AN522:

    --- Quote Start ---

    In Stratix III and Stratix IV devices, BLVDS interface can be implemented using 2.5-V Differential SSTL Class I or II, depending on the current strength requirement.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    > Pseudo-differential operated single-ended buffers with serial termination have to be used instead.

    I have a similar problem: The Synthesis reports:

    Warning: Pin OUTPUTp[0] must use pseudo-differential I/O standard -- the Fitter will automatically assign LVDS_E_3R pseudo-differential I/O standard to pin

    And later it says:

    Error: The differential I/O standard LVDS_E_3R cannot be used on the pin OUTPUTp[0], because the specified pin uses a tri-stated output buffer.

    How do I have to setup these pins in the assignment editor?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    To better understand your setup, what's connected to the pseudo differential pin in your design?