Honored Contributor
Honored ContributorI finally got it working at 40 Meg Samples per sec i.e. 480 Mbits/sec. Using DDIO_IN along with proper timing constrains was the key. DDRIO_IN gave me two streams of data each of which was 240 Mbps. i used the Bit Clock (240 MHz) for DDRIO and the used Bit Clk/2 to further split the two 240 Mbs streams into 4 streams of 120 mbps. After that i used four shift registers (self designed, not LPM_SHIFTREG megafunction) to convert serial streams to parallel. Self designed shift registers saved resources and gave me more control along with better results.
Another thing was not to use the Frame Clock( 40 MHz) for final laching of data. Frame clock was not working for me at all as it was latching the coroupt data. ( no idea why? theoraticaly it should have been a 50% dudy cycle wave but my guess is that its duty cycle was not consistant). i used a self genrated signal of 40 Mhz with a duty cycle of 33 %. its edges were syncronous with Bit Clock and the low to hight transition accoured after the posedge of Frame clock so that i can allign my data (frame clock was used as a reference point, not to drive latches itself). this provided me with the right timing to latch the final 12 bits. my advise to others is that if u are tring to do some thing like this, try using dedicated clock pins and make use of ALTLVDS megafunction. this will make your life much more easier. Thanks to those who helped me out.
