Stratix III EP3SL340c3 Diffrential IO data rate

Timing constraints are a must. Without them you're really designing blind, as RTL is dependent on the fact that timing is met.

Are the clock and data coming in edge-aligned or center-aligned? If it's center-aligned, then do the following:

create_clock -period 1.666 -name adc_clk [get_ports adc_clk]

create_clock -period 1.666 -name adc_clk_ext -waveform {0.833 1.666};# This is a virtual clock, not assigned to anything physical

set_input_delay -clock adc_clk_ext -max 0.0 [get_ports adc_data*]

set_input_delay -clock adc_clk_ext -min 0.0 [get_ports adc_data*]

Naturally change the port names to match your design. This creates a 1.666ns clock coming into the FPGA. It creates a virtual clock that represents the clock at the ADC. I've used -waveform to say it's shifted by 180 degrees(i.e. it's center aligned). The set_input_delay requirements say there is an external register clocked by this virtual clock that sends data to the FPGA in 0ns. Ignoring the 0ns for now, what you'll see is you have 0.833ns setup requirement and -0.833ns hold requirement, i.e. if the data is skewed in relation to the clock by more than 0.8333ns, then it will fail timing. This gives the whole data eye to the FPGA to play with. If you know how much skew the ADC adds and the board, then change it there, i.e. if it adds +/- 200ps of skew, then make the max value 0.2 and the min value -0.2.

If they're edge aligned, then you don't do that -waveform option(it will default to rising edge at 0 and falling at 50% duty cycle).

As for the altlvds, don't use it since you can't use the dedicated hardware. Just use an altddio_in to use the DDR input registers, which gets you down to 300mbits. Then write some code to do another 2:1 mux with registers, getting it down to 150MHz, which is a feasible speed. Although that brings up another question, if you have 12 300MHz clocks coming in, and they're not all on PLLs, you can't just create 150MHz domains. You'll probably want to create a toggling clock enable(search forum for discussions on this) to enable the 300MHz clock every other cycle. Then you'll need FIFOs to get everything together. But that's all later, as you need to make sure you can meet timing on the 600mbps data coming into the IO registers.