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Altera_Forum
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16 years ago

Stratix III EP3SL340c3 Diffrential IO data rate

Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega...
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Altera_Forum
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16 years ago

Hey FvM,

The problems with HSTC is that these four connectors have a combined 8 Dedicated clock pins (on reciever side) whereas i need 12x2= 24 (12 adc and each having 2 clocks). lets assume i get past this issue using IO pins, i will need a 16.66% duty cycle, 25MHz signal for "tx_enable" whereas one from ADC is 50% duty cycle and 50 MHz. I am still not convinced if i can use a SERDES/ALTLVDS megafunction.