Stratix III EP3SL340c3 Diffrential IO data rate

I didn't realize, that DE3 is using Stratix III rather than Cyclone III. The points I mentioned about user designed software SERDES are basically valid for Stratix III, that also has DDIO capabilities in IO cells. But there are also interesting options provided by the Stratix III hardware SERDES with DPA function.

As you pointed out, you can't use individual PLLs with 12 ADC. As far as I see, there are some dedicated clock inputs at the HSTC connectors. So the SERDES can use either the ADC input clock inside the FPGA or the FCO from one ADC. The phase should be adjusted individually for each ADC. DPA would allow an adjustment of each individual ADC output. In this case, delay skew caused by DE3 board and external wiring could be cancelled.