Honored Contributor
Honored ContributorHey Rysc
Well, it is a C3 speed grade device so it is not the fastest available. I agree completely with what you have said about routing and fitter. Unfortunately i cant use the luxury of PLLs in the device otherwise things would have been easier. Quoting "If you're timing constraints are correct, then the Quartus II fitter will modify the delay chains on the input registers to center the data onto the clock edge, but it can only do so much." Well this is where i am not sure if my timing constraints are right. Initially I was using classic timing analyzer because of its simplicity. Simulation showed things working even at IO rate of 600Mbps. When I tried TimeQuest timing analyzer ( and to be honest, guessed some of the constrains) the output got messed up. To get the valid constraints, i tried going through Device datasheets but a lot of stuff there was ambiguous and went over my head. Is getting the constraints right my only chance or i can try some thing different. It might sound crazy but someone suggested that i should try to get it to LUT level and implement stuff (equations!!!) there. I have no idea how to do that but again if all the problems are because of IO/clock missalignments due to different nonconstant delays, things in LUT will get messed up anyways... Regards
