Honored Contributor
Honored ContributorWhat speed grade device is on the DE3 board? 600Mbps on an input port is pretty fast, as you've only got a 1.666ns bit period.
My second concern is that, being limited by the board you're using, a number of the clocks will be coming in on regular I/O. That means you're going to use local routing to get to all the I/O in the databus, which means the delay to every I/O will be different. If you're timing constraints are correct, then the Quartus II fitter will modify the delay chains on the input registers to center the data onto the clock edge, but it can only do so much. My third concern is that, without a PLL, you're raw clock delay variance will be too large. For example, let's say it takes 3ns for the clock to route to the I/O, which is pretty fast. That's 3ns in the slow corner timing model. In the fast corner model it could easily be half that, especially in the slowest speed grade, so that means your clock delay could vary between 1.5ns and 3ns over PVT, which is pretty much the whole data eye. I'm making these numbers up, but you get the point. A PLL's feedback loop is designed to eliminate PVT variance on the clock tree, which makes I/O timing on fast interfaces much more feasible. So I don't think it's a logical issue, but a timing issue, that will be the problem. I haven't built anythign up and tested it out, but have serious concerns. Let me know if any of that doesn't make sense.
