Stratix III EP3SL340c3 Diffrential IO data rate

Hi FvM,

Unfortunately i cant use 1 PLL with multiple ADCs as each ADC is on a separate board with its own connector. I have designed a Back Plane PCB which splits each HSTC Connector's IO pins only (no dedicated clock pins) to 3 small connectors (for 3 ADC). Thus 4 HSTCs provide me with 12 connectors for ADCs, none of which share pins on the FPGA. Also HSTC on DE3 has only 4 dedicated clock pins (thats y i didnt use them) and quartus wont let me connect PLL to a normal IO pin.

"Alternatively, you can use the bitclock output from ADC as SERDES clock and no PLL at all."

Well this might work. Only worry i have is if the Bitclock will have enough fanout to support SERDES as it is using a normal IO pin instead of a dedicated clock pin.

EDIT

"Hmmm. Just tried ALTLVDS megafunction. The slow clock has a dutycycle recuirement of 8.33%. One from my ADC is 50%. So i dont know if this approach will work..."

Thanks