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Honored Contributor
Honored ContributorStratix III EP3SL340c3 Diffrential IO data rate
Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega...
Altera_ForumHonored Contributor
Honored ContributorI don't think, that you need a PLL for each ADC. You may use a PLL output for each ADC, if you want to adjust the receiving phase for each ADC individually, which shouldn't be necessary normally. At least, you should provide a common phase adjustment for the fast SERDES clock (300 MHz) for all ADCs. Alternatively, you can use the bitclock output from ADC as SERDES clock and no PLL at all. Personally, I prefer the PLL variant.
The SERDES should use an altddio_in block as 1:2 demux. Than a single SR, shifting in two bits for each fastclock edge, can be used. It has no problem to achieve 600 MBPS rate with CIII. A user designed SERDES can provide deserialization factors, that aren't directly supported by the altlvds MegaFuntion with CIII, e.g. 12 and 14. It also allows a clearer configuration of timing parameters. P.S.: Utilizing the test pattern option of LVDS ADC and PLL dynamic phase shift, an automatic SERDES phase calibration can be realized.
