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Altera_Forum
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18 years ago

Stratix II VCCSEL connection

How should I time VCCSEL of my Stratix II if VCCIO of Bank 3 is 1.8V and the configuration voltage requirements are 3.3V?
Altera_Forum's avatar
Altera_Forum
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18 years ago

If the VCCIO of I/O bank 3 is powered by 1.5 or 1.8-V and the configuration signals used require 3.3- or 2.5-V signaling, you should connect VCCSEL to VCCPD in order to enable the 1.8V/1.5V input buffers for configuration. The 1.8-V/ 1.5-V input buffers are 3.3-V tolerant. This will also enable the FPGA to exit POR under these conditions.