Stratix II top / bottom bank LVDS inputs

You can have LVDS inputs on the dedicated clock pins, but they don't have the SERDES circuitry that the side banks have.

There are a total of 4 dedicated input clock pin pairs on top banks and a total of 4 dedicated clock pin pairs on the bottom banks.

The top and bottom banks can't support LVDS toggle rates as high as what the side I/O banks can support, and they don’t have differential termination resistors. They are useful for getting differential clocks to the enhanced PLLs.