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Altera_Forum
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18 years ago

Stratix II PLL and crossing clock domains

Hi, I want to transfer data between two clock domains(12 MHz to 20 MHz). I am using a Stratix II FPGA PLL to generate both clocks from a 100 MHz clock. I need that the first rising...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

As I said. By defining a 4 MHz clock in the same PLL. Each edge of it is aligned with both other clocks. All PLL clocks (with zero phase shift) are initially aligned at a PLL reset.