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Altera_Forum
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18 years ago

Stratix II PLL and crossing clock domains

Hi, I want to transfer data between two clock domains(12 MHz to 20 MHz). I am using a Stratix II FPGA PLL to generate both clocks from a 100 MHz clock. I need that the first rising...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I need to pass 48 (14 bit each) symbols at 12 MHZ from a QPSK mapper, to 64 (14 bit each) subcarriers at 20 MHz as input to an IFFT. Including the GI, output frame has a length of 80

80/20MHz=48/12MHz= 4 us.

I'm using this in a personal OFDM processor project.

I only need synchronize both clocks (align first rising edge) in order to clock two counters (mod 48 and mod 80).

How can i detect the moment in that the two clock rising edges are aligned? How to implement this phase detector using the stratix ii embeded PLLs?

Thanks